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FEATURES +3 V Supply Voltage Baseband Serial Port (BSPORT) Differential IRx and QRx ADC Channels Two 15-Bit Sigma-Delta A/D Converters FIR Digital Filters 64 dB SNR Output Word Rate 270.83 kHz Twos Complement Coding On-Chip Offset Calibration Power-Down Mode Auxiliary D/A Converter Auxiliary Serial Port (ASPORT) On-Chip Voltage Reference Low Power 28-Lead TSSOP/28-Lead SOIC APPLICATIONS GSM Basestations Pagers FUNCTIONAL BLOCK DIAGRAM
DVDD2 DVDD1 DGND AGND AVDD1
Dual Sigma-Delta ADC with Auxiliary DAC AD7729
GENERAL DESCRIPTION
This monolithic 3 V CMOS device is a low power, two-channel, input port with signal conditioning. The receive path is composed of two high performance sigma-delta ADCs with digital filtering. A common bandgap reference feeds the ADCs. A control DAC is included for such functions as AFC. The auxiliary functions can be accessed via the auxiliary port (ASPORT). This device is available in a 28-lead TSSOP package or a 28-lead SOIC package.
AVDD2
ASDI ASDIFS ASCLK ASDO ASDOFS ASE AUXILIARY SERIAL INTERFACE 10-BIT AUXDAC AUXDAC
BSDI BSDIFS BSCLK BSDO BSDOFS BSE BASEBAND SERIAL INTERFACE
OFFSET ADJUST
DECIMATION FIR DIGITAL FILTER
IRxP MODULATOR IRxN
OFFSET ADJUST
DECIMATION FIR DIGITAL FILTER
QRxP MODULATOR QRxN
DIVIDE BY 2 MCLK RxON RESETB MUX REFERENCE REFCAP REFOUT
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
V 10%; DVDD1 = DVDD2 AD7729-SPECIFICATIONS1 (AVDD1T==AVDD2to=T+3 unless otherwise noted) = +3 V 0 V, f = 13 MHz; RxPOWER1 = 0; RxPOWER0 = 1; MCLKDIV = 0; T
CLK A MIN MAX
10%; DGND = AGND =
Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Absolute Voltage, VREFOUT REFOUT TC ADC CHANNEL SPECIFICATIONS Resolution ADC Signal Range VBIAS Differential Signal Range Single-Ended Signal Range Input Sample Rate Output Word Rate DC Accuracy Precalibration Offset Error Post Calibration Offset Error Post Calibration Offset Error TC Input Resistance (DC) Input Capacitance Dynamic Specifications Dynamic Range Signal to (Noise + Distortion) Gain Error Gain Match Between Channels Filter Settling Time Frequency Response 0 kHz-70 kHz 85 kHz 96 kHz 135 kHz >170 kHz Absolute Group Delay Group Delay Between Channels (0 kHz-96 kHz) Coding AUXILIARY CONVERTER2 Resolution Output Range Code 000 Offset Error Code 3FF Gain Error DC Accuracy Integral Nonlinearity Differential Nonlinearity Update Rate Load Resistance Load Capacitance ISINK Full-Scale Settling Time LSB Settling Time Coding
AD7729A
Units
Test Conditions/Comments
1.3 5% 50 1.3 10% 50 15 2 VREFCAP VREFCAP/2 to (AVDD - VREFCAP /2) VREFCAP to (AVDD - VREFCAP ) VBIAS V REFCAP/2 VBIAS V REFCAP 13 270.83 45 10 50 1.23 10 67 64 1 0.5 0.2 47 0.05 -1 -3.0 -55 -55 23 5 Twos Complement
V min/max ppm/C typ V min/max ppm/C typ Bits V p-p Volts Volts V min/max V min/max MSPS kHz mV typ mV max V/C typ M typ pF typ dB typ dB min dB max dB max dB max s typ dB max/min dB max dB max dB max dB max s typ ns typ
0.1 F Capacitor Required from REFCAP to AGND
0.1 F Capacitor Required from REFOUT to AGND RxON = 1
Differential Single-Ended For Both Positive and Negative Analog Inputs For Positive Analog Inputs; Negative Analog Inputs = VBIAS
TC = Temperature Coefficient
Input Frequency = 67.7 kHz
Input Frequency = 67.7 kHz, wrt 1.3 V Input Frequency = 67.7 kHz, wrt VREFCAP
Does Not Include Input Antialias RC Circuit
10 2/32 x VREFCAP 35 2 VREFCAP -60 +100
Bits V mV max V mV min mV max Maximum Output for Specified Accuracy = AVDD - 0.2 V or 2.6 V, Whichever Is Lower
4 2 540 10 50 50 4 2 Binary
LSB max LSB max kHz max k min pF max A typ s typ s typ
Guaranteed Monotonic to 9 Bits See Figure 1 See Figure 1
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Parameter LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage IOZL, Low Level Output Three-State Leakage Current IOZH, High Level Output Three-State Leakage Current POWER SUPPLIES AVDD1, AVDD2 DVDD1, DVDD2 IDD AD7729A Units Test Conditions/Comments VDD - 0.8 0.8 10 10 VDD - 0.4 0.4 10 10 V min V max A max pF max V min V max A max A max V min/max V min/max See Table I |IOUT| < 100 A |IOUT| < 100 A
2.7/3.3 2.7/3.3
NOTES 1 Operating Temperature Range: -40C to +105C. Therefore, T MIN = -40C and TMAX = +105C. 2 During power-down, the AUXDAC has an output resistance of 30 k approximately to AGND. Specifications subject to change without notice.
CL 50pF
RL 10k
Figure 1. AUXDAC Load Equivalent Circuit
Table I. Current Summary (AVDD1 = AVDD2 = DVDD1 = DVDD2 = +3.3 V, RxPOWER1 = 0, RxPOWER0 = 1)
Internal Analog Digital Current Current (typ) (typ) 4.2 2 0.7 1 0.0001 0.0001 3.4 0.86 0.0001 0.0001 0.04 0.0001 External Interface Total Current Current (typ) (max) 4 0.1 0.002 0.002 0.015 0.005 13.5 3.4 1.1 1.7 0.1 0.05
Conditions ADCs On Only AUXDAC On Only REFCAP On Only REFCAP and REFOUT On Only All Sections Off All Sections Off
BSE 1 0 0 0 0 0
ASE 0 1 0 0 0 0
MCLK ON YES YES NO NO YES NO
Comments REFOUT Enabled, BSCLK = MCLK REFOUT Disabled, ASCLK = MCLK/48 REFOUT Disabled REFOUT Enabled MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA.
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Table II. Receive Section Signal Ranges Table III. Auxiliary Section Signal Ranges
Baseband Section VREFCAP VREFOUT ADC ADC Signal Range VBIAS Differential Input Single-Ended Input Signal Range Differential Single-Ended
Signal Range 1.3 V 5% 1.3 V 10% 2 VREFCAP VREFCAP/2 to (AVDD1 - VREFCAP/2) VREFCAP to (AVDD1 - VREFCAP) VBIAS VREFCAP/2 VBIAS VREFCAP
AUXDAC Output Code Code 000 Code 3FF
Signal Range 2/32 x VREFCAP 2 VREFCAP
TIMING CHARACTERISTICS
Parameter AUXILIARY FUNCTIONS Clock Signals t1 t2 t3 t4 t5 t6 t10 t11 t12 t13 t14 t15 t16 t17 Receive Section Clock Signals t7 t8 t9 t18 t19 t20 t21 t22 t23 t24 t25
(AVDD1 = AVDD2 = +3 V 10%; DVDD1 = DVDD2 = +3 V TA = TMIN to TMAX , unless otherwise noted)
Units Description
10%; AGND = DGND = 0 V;
Limit at TA = -40 C to +105 C
76 30.4 30.4 t1 0.4 x t1 0.4 x t1 20 10 15 0 0 15 10 t4 + 15
ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns max ns min ns min
See Figure 2. MCLK Period MCLK Width Low MCLK Width High ASCLK Period. See Figures 4 and 6. ASCLK Width Low ASCLK Width High ASDI/ASDIFS Setup Before ASCLK Low ASDI/ASDIFS Hold After ASCLK Low ASDOFS Delay from ASCLK High ASDOFS Hold After ASCLK High ASDO Hold After ASCLK High ASDO Delay from ASCLK High ASDIFS Low to ASDI LSB Read by ASPORT Interval Between Consecutive ASDIFS Pulses See Figures 5 and 7. BSCLK Period BSCLK Width Low BSCLK Width High BSDI/BSDIFS Setup Before BSCLK Low BSDI/BSDIFS HoldAfter BSCLK Low BSDOFS Delay from BSCLK High BSDOFS Hold After BSCLK High BSDO Hold After BSCLK High BSDO Delay from BSCLK High BSDIFS Low to ASDI LSB Read by BSPORT Interval Between Consecutive BSDIFS Pulses
t1 0.4 x t1 0.4 x t1 20 10 15 0 0 15 10 t7 + 15
ns min ns min ns min ns min ns min ns max ns min ns min ns max ns min ns min
ASCLK = MCLK/(2 x ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz. BSCLK = MCLK/(2 x BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz. Specifications subject to change without notice.
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AD7729 TIMING DIAGRAMS
t1 t1 t3
*ASCLK MCLK
t3
t2
t5 t6 t4
t2
*ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 2. Clock Timing
100 A IOL MCLK TO OUTPUT PIN CL 15pF 100 A IOH *BSCLK +2.1V
Figure 4. ASCLK
t1 t3 t2
t8 t9 t7
Figure 3. Load Circuit for Timing Specifications
*BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 5. BSCLK
ASE (I) ASCLK (O) THREE-STATE
t 10 t 16
ASDIFS (I)
t 17
t 11 t 10
ASDI (I) THREE-STATE ASDOFS (O) THREE-STATE D9
t 11
D8 A1 A0 D9 D8 D7
t 12
t 13 t 14
D9 A2 A1 A0 D9 D8
ASDO (O)
NOTE I = INPUT, O = OUTPUT
t 15
Figure 6. Auxiliary Serial Port ASPORT
BSE (I) THREE-STATE
BSCLK (O)
t 18 t 24
BSDIFS (I)
t 25
t 19
BSDI (I) THREE-STATE BSDOFS (O) THREE-STATE BSDO (O) NOTE I = INPUT, O = OUTPUT D9
t 18
t 19
D8 A1 A0 D9 D8 D7
t 20
t 21 t 22
D9 A2 A1 A0 D9 D8
t 23
Figure 7. Baseband Serial Port BSPORT
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ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise stated)
ORDERING GUIDE
AVDD, DVDD to GND . . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +150C TSSOP JA Thermal Impedance . . . . . . . . . . . . . . . . . . . +122C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220C SOIC JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +72C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Model AD7729AR
Temperature Range
Package Descriptions
Package Options
-40C to +105C Small Outline IC R-28 (SOIC) AD7729ARU -40C to +105C Thin Shrink Small RU-28 Outline (TSSOP)
PIN CONFIGURATION
IRxP IRxN QRxP QRxN AVDD2 AVDD1 AGND ASDIFS ASDI
1 2 3 4 5 6 7 8 9 28 27 26 25 24
REFCAP REFOUT AUXDAC DVDD1 DVDD2 DGND
AD7729
23 22
ASE TOP VIEW (Not to Scale) 21 ASDOFS
20 19 18 17 16 15
ASDO BSE BSDOFS BSDO BSCLK MCLK
ASCLK 10 BSDIFS 11 BSDI 12 RESETB 13 RxON 14
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7729 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN FUNCTION DESCRIPTIONS
Pin Number 15 13
Mnemonic MCLK RESETB
Function Master Clock Input. MCLK is driven from a 13 MHz crystal. The active levels for MCLK are determined by the value of DVDD2. Active Low Reset Signal. This input resets the entire AD7729 chip, resetting the control registers and clearing the digital filters. The logic input levels (VINH and VINL) for RESETB are determined by the value of DVDD2. Analog Power Supply Connection for the Rx Section and the Bandgap Reference. Analog Power Supply Connection for the Auxiliary Section. Analog Ground Connection. Digital Power Supply Connection. Digital Power Supply Connection for the Serial Interface Section. This power supply also sets the threshold voltages for RxON, RESETB and MCLK. Digital Ground Connection. Differential Analog Input for I Receive Channel. Differential Analog Input for Q Receive Channel. Analog Output Voltage from the 10-Bit Auxiliary DAC AUXDAC. This DAC is used for functions such as Automatic Gain Control (AGC). The DAC possesses a register that is accessible via the ASPORT or BSPORT. The DAC may be individually powered down. A bypass capacitor to AGND of 0.1 F is required for the on-chip reference. The capacitor should be fixed to this pin. Buffered Reference Output, which has a nominal value of 1.3 V. A bypass capacitor (to AGND) of 0.1 F is required on this pin. Serial Clock used to clock data or control bits to and from the auxiliary serial port (ASPORT). The frequency of ASCLK is programmable and is equal to the frequency of the master clock (MCLK) divided by an integer number. Serial Data Input of ASPORT. Both data and control information are input on this pin. Input Framing Signal for ASDI Serial Transfers. Serial Data Output of ASPORT. Both data and control information are output on this pin. ASDO is in three-state when no information is being transmitted, thereby allowing external control. Output Framing Signal for ASDO Serial Transfers. ASPORT Enable. When ASE is low, the ASPORT is put into three-state thereby allowing external control of the serial bus. Output serial clock used to clock data or control bits to and from the baseband serial port (BSPORT). The frequency of BSCLK is programmable and is equal to the frequency of the master clock (MCLK) divided by an integer number. Serial Data Input of BSPORT. Both data and control information are input on this pin. Input Framing Signal for BSDI Serial Transfers. Serial Data Output of BSPORT. Both data and control information are output on this pin. BSDO is in three-state when no information is being transmitted, thereby allowing external control. Output Framing Signal for BSDO Serial Transfers. BSPORT Enable. When BSE is low, the BSPORT is put into three-state thereby allowing external control of the serial bus. Receive Section Power-On Digital Input. The receive section is powered up by taking pin RxON high. The receive section can alternatively be powered up by programming bit RxON in baseband control register BCRA. When the powering up/down of the receive section is being controlled by pin RxON, bit RxON should equal zero. Similarly, when the powering up/ down of the receive section is being controlled by bit RxON, pin RxON should be tied low. The logic input levels (VINH and VINL) for RxON are determined by the value of DVDD2. -7-
Power Supply 6 5 7 25 24 23
AVDD1 AVDD2 AGND DVDD1 DVDD2 DGND
Analog Signal and Reference 1, 2 IRxP, IRxN 3, 4 QRxP, QRxN 26 AUXDAC
28 27
REFCAP REFOUT
Auxiliary Serial Port (ASPORT) 10 ASCLK
9 8 20
ASDI ASDIFS ASDO
21 22
ASDOFS ASE
Baseband Serial Port (BSPORT) 16 BSCLK
12 11 17
BSDI BSDIFS BSDO
18 19 ADCs 14
BSDOFS BSE RxON
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TERMINOLOGY Absolute Group Delay Output Rate
Absolute group delay is the rate of change of phase versus frequency, do/df. It is expressed in microseconds.
Differential Nonlinearity
This is the rate at which data words are made available (270.833 kHz).
Offset Error
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the DAC or ADC.
Dynamic Range
This is the amount of offset, wrt VREF in the auxiliary DAC and is expressed in mVs.
Output Signal Span
This is the output signal range for the auxiliary DAC section.
Sampling Rate
Dynamic Range is the ratio of the maximum output signal to the smallest output signal the converter can produce (1 LSB), expressed logarithmically, in decibels (dB = 201og10 (ratio)). For an N-bit converter, the ratio is theoretically very nearly equal to 2N (in dB, 20Nlog10(2) = 6.02N). However, this theoretical value is degraded by converter noise and inaccuracies in the LSB weight.
Gain Error
This is the rate at which the modulators on the receive channels sample the analog input.
Settling Time
This is the digital filter settling time in the AD7729 receive section. On initial power-up or after returning from the powerdown mode, it is necessary to wait this amount of time to get useful data.
Signal Input Span
This is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. In the AD7729, gain error is specified for the auxiliary section.
Gain Matching Between Channels
The input signal range for the I and Q channels is biased about VREF.
Signal to (Noise + Distortion) Ratio
This is the gain matching between the IRx and QRx channel and is expressed in dBs.
Group Delay Between Channels
This is the difference between the group delay of the I and Q channels and is a measure of the phase matching characteristics of the two.
Integral Nonlinearity
This is the measured ratio of signal to (noise + distortion) at the output of the receive channel. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for a sine wave is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB
This is the maximum deviation from a straight line passing through the endpoints of the auxiliary DAC transfer function.
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FUNCTIONAL DESCRIPTION
BASEBAND CODEC Receive Section
4.7k IRx 4.7k 100pF 100pF IRxN IRxP I CHANNEL
AD7729
The receive section consists of I and Q receive channels, each comprising of a simple switched-capacitor filter followed by a 15-bit sigma-delta ADC. On-board digital filters, which form part of the sigma-delta ADCs, also perform critical system-level filtering. Their amplitude and phase response characteristics provide excellent adjacent channel rejection. The receive section is also provided with a low power sleep mode to place the receive section on standby between receive bursts, drawing only minimal current.
Switched Capacitor Input
4.7k QRx 4.7k 100pF 100pF
QRxP Q CHANNEL QRxN
The receive section analog front-end is sampled at 13 MHz by a switched-capacitor filter. The filter has a zero at 6.5 MHz as shown in Figure 8a. The receive channel also contains a digital low-pass filter (further details are contained in the following section) which operates at a clock frequency of 6.5 MHz. Due to the sampling nature of the digital filter, the passband is repeated about the operating clock frequency and at multiples of the clock frequency (Figure 8b). Because the first null of the switched-capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dBs (Figure 8c), further simplifying the external antialiasing requirements (see Figures 9 and 10).
0 dBs FRONT-END ANALOG FILTER TRANSFER FUNCTION 6.5 13 19.5
REFOUT TO INPUT BIAS CIRCUITRY 0.1 F 0.1 F REFCAP VOLTAGE REFERENCE
Figure 9. Example Circuit for Differential Input
Figure 10 shows the recommended single-ended analog input circuit.
AD7729
MHz
IRx
4.7k 100pF
IRxP I CHANNEL IRxN
a) Switched-Cap Filter Frequency Response
0 dBs QRx DIGITAL FILTER TRANSFER FUNCTION 6.5 13 19.5
4.7k 100pF
QRxP Q CHANNEL
MHz
QRxN
b) Digital Filter Frequency Response
VBIAS 0 dBs SYSTEM FILTER TRANSFER FUNCTION 6.5 13 19.5 HIGH SPEED BUFFER 0.1 F MHz 0.1 F REFCAP VOLTAGE REFERENCE REFOUT
c) Overall System Response of the Receive Channel Figure 8.
Figure 10. Example Circuit for Single-Ended Input
The circuitry of Figure 9 implements first-order low-pass filters with a 3 dB point at 338 kHz; these are the only filters that must be implemented external to the baseband section to prevent aliasing of the sampled signal.
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VBIAS + VREF/2 IRxN QRxN
The digital filter that follows the modulator removes the large out-of-band quantization noise (Figure 13c), while converting the digital pulse train into parallel 15-bit-wide binary data. The 15-bit I and Q data, which is in twos complement format, is made available via a serial port.
VOLTAGE
VBIAS
IRxP QRxP VBIAS - VREF/2
QUANTIZATION NOISE BAND OF INTEREST FS/2 3.25MHz
a) Effect of High Oversampling Ratio
10 ... 00 00 ... 00 ADC CODE 01 ... 11
Figure 11. ADC Transfer Function for Differential Operation
NOISE SHAPING VBIAS + VREF BAND OF INTEREST IRxN QRxN FS/2 3.25MHz
VOLTAGE
VBIAS
b) Use of Noise Shaping to Further Improve SNR
IRxP QRxP
VBIAS - VREF
DIGITAL FILTER CUTOFF FREQUENCY = 100kHz
BAND OF INTEREST 10 ... 00 00 ... 00 ADC CODE 01 ... 11
FS/2 3.25MHz
Figure 12. ADC Transfer Function for Single-Ended Operation
Sigma-Delta ADC
c) Use of Digital Filtering to Remove the Outof-Band Quantization Noise Figure 13.
Digital Filter
The AD7729 receive channels employ a sigma-delta conversion technique, which provides a high-resolution 15-bit output for both I and Q channels with system filtering being implemented on-chip. The output of the switched-capacitor filter is continuously sampled at 6.5 MHz (master clock/2), by a charge-balanced modulator, and is converted into a digital pulse train whose duty cycle contains the digital information. Due to the high oversampling rate, which spreads the quantization noise from 0 MHz to 3.25 MHz (FS/2), the noise energy contained in the band of interest is reduced (Figure 13a). To reduce the quantization noise still further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (Figure 13b).
The digital filters used in the AD7729 receive section carry out two important functions. Firstly, they remove the out-of-band quantization noise which is shaped by the analog modulator. Secondly, they are also designed to perform system level filtering, providing excellent rejection of the neighboring channels. Digital filtering has certain advantages over analog filtering. Firstly, since digital filtering occurs after the A/D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Secondly, the digital filter combines low passband ripple with a steep roll-off, while also maintaining a linear phase response. This is very difficult to achieve with analog filters. However, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full-scale have the potential to saturate the analog modulator, even though the average value of the signal is within limits. To alleviate this problem, the AD7729 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 100 mV.
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10 0 -10 -20 -30 GAIN - dB -40 -50 -60 -70 -80 -90 -100 -110 -120 0 50 100 150 200 FREQUENCY - kHz 250 300
the RxON bit or the RxON pin high, 36 symbol periods are allowed for the analog and digital circuitry to settle. An internal timer then times out a time equal to RxDELAY1. When RxDELAY1 has expired, the AD7729 offset calibration routine begins, assuming the RxAUTOCAL bit in control register BCRA is equal to 1. If RxAUTOCAL equals zero, no calibration occurs and T2 in Figure 16 equals zero. In internal autocalibration mode, the AD7729 internally disconnects the differential inputs from the input pins and shorts the inputs to measure the resulting ADC offset. In external autocalibration mode, the inputs remain connected to the pins, allowing system offsets along with the AD7729 internal offsets to be evaluated. This is then averaged 16 times to reduce noise and the averaged result is then placed in the offset register. The input to the ADC is then switched back for normal operation and the analog circuitry and digital filter are permitted to settle. This time period is included in TCALIBRATE, which equals 40 x 48 MCLK cycles.
RxON
Figure 14. Digital Filter Frequency Response
Filter Characteristics
The digital filter is a 288-tap FIR filter, clocked at half the master clock frequency. The 3 dB point is at 96 kHz. Due to the low-pass nature of the receive filters, a settling time is associated with step input functions. Output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. Hence the AD7729 digital filters have a settling time of 44.7 s (288 x 2t1).
Receive Offset Calibration
T0
T1
T2
T3
T0 = TSETTLE = 36
48 MCLKs FIRST VALID OUTPUT WORD HERE
T1 = RxDELAY1 = 0...255 48 MCLKs T2 = TCALIBRATE = 40 48 MCLKs T3 = RxDELAY2 = 0...255 48 MCLKs
Included in the digital filter is a means by which receive offsets may be calibrated out. Each channel of the digital low-pass filter section has an offset register. The offset register can be made to contain a value representing the dc offset of the preceding analog circuitry. In normal operation, the value stored in the offset register is subtracted from the filter output data before the data appears on the serial output pin. By so doing, dc offsets in the I and Q channels are calibrated out. Autocalibration or usercalibration can be selected. Internal autocalibration will remove internal offsets only while user calibration allows the user to write to the offset register in order to also remove external offsets. The offset registers have enough resolution to hold the value of any dc offset between 162.5 mV (1/8th of the input range). Offsets larger than 162.5 mV will cause a spurious result due to calibration overrange. However, the performance of the sigmadelta modulators will degrade if full-scale signals with more than 100 mV of offset are experienced. The 10-bit offset register represents a twos complement value. The LSB of the offset registers corresponds to Bit 3 of the Rx words while the MSB of the offset registers corresponds to Bit 12 of the Rx words (see Figure 15).
RxDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 16. Data Rx Procedure
After calibration is complete, a second timer is started which times out a time equal to RxDELAY2. The range of both RxDELAY1 and RxDELAY2 is 0 to 255 units where each unit equals one bit time. Therefore, the maximum delay time is 255 x 1/270 kHz = 941.55 s. As soon as RxDELAY2 has expired, valid output words appear at the output. The Rx data will be 15 bits wide.
ASDOFS BSDOFS
ASDO BSDO
VALID I DATA
I FLAG
VALID Q DATA
Q FLAG
T1 I WORD T1 = 16 MCLKs T2 = 8 MCLKs
T2
T1 Q WORD
T2
Figure 17. ASDO/BSDO in Rx Mode
Receive Offset Adjust: User Calibration
OFFSET REGISTER
9
8
7
6
5
4
3
2
1
0
Figure 15. Position of the 10-Bit Offset Word
Receive Offset Adjust: Autocalibration
If receive autocalibration is selected, the AD7729 will initiate an autocalibration routine each time the receive path is brought out of the low power sleep mode. After RxON is asserted, by taking
When user calibration is selected, the receive offset register can be written to, allowing offsets in the IF/RF demodulation circuitry to be calibrated out also. However, the user is now responsible for calibrating out receive offsets belonging to the AD7729. When the receive path enters the low power mode, the registers remain valid. After powering up, the first IQ sample pair is output once time has elapsed for both the analog circuitry to settle and also for the output of the digital filter to settle.
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Figure 18 shows a flow diagram for calibration of the receive section.
Voltage Reference
The reference of the AD7729, REFCAP, is a bandgap reference which provides a low noise, temperature compensated reference to the IQ receive ADCs and the AUXDAC. The reference is also made available on the REFOUT pin. The reference has a value of 1.3 V nominal. When the AD7729 is powered down, the reference can also be powered down. Alternatively, by setting bit LP to 1, the reference remains powered up. This is useful as the power-up time for the receive section and auxiliary converter is reduced since the reference does not require time to power up and settle.
0
RxON
1
1
RxAUTOCAL
0
Baseband and Auxiliary Serial Ports (BSPORT and ASPORT)
TSETTLE 1 RxEXTCAL 0 RxDELAY1 RESETS TO ZERO CAN HAVE A VALUE OF 0...255 48 MCLKs
Both the baseband and auxiliary SPORTs are DSP compatible serial ports which provide access to the 27 on-chip registers as illustrated in Table IV. Since some registers are accessible over both the auxiliary and baseband SPORTs, the user can decide which registers will be accessible over which SPORT, this feature providing maximum flexibility for the system designer. The user also has the ability to adjust the frequency of the SCLKs in each SPORT, which is useful for power dissipation minimization. Furthermore, it is possible for the user to access all the ADC and AUXDAC control registers over one SPORT, the other SPORT being disabled by tying its serial port enable (SE) low. This feature is useful when the user has only one SPORT available for communication with the AD7729.
Resetting the AD7729
CONNECT ADC INPUTS
SHORT ADC INPUTS
COUNTER RESETS TO 36 (36 48 MCLKs) TO ALLOW FOR FILTER SETTLING TIME TSETTLE RxDELAY1 40 48 MCLK TCALIBRATE
RxDELAY2 RESETS TO ZERO. CAN HAVE A VALUE OF 0...255 48 MCLKs
RxREADY
Figure 18. Receive Offset Adjust
Auxiliary Control Functions
The AD7729 also contains an auxiliary DAC that may be used for AGC. This 10-bit DAC consists of high impedance current sources, designed to operate at very low currents while maintaining its dc accuracy. The DAC is buffered by an output amplifier and allows a load of 10 k. The DAC has a specified output range of 2 x VREFCAP /32 to 2 x VREFCAP. The analog output is: 2 VREFCAP /32 + (2 VREFCAP - 2 VREFCAP /32) x DAC/1023 where DAC is the 10-bit digital word loaded into the DAC register. To perform a conversion, the DAC is first powered up using the AUXDACON bit in control register ACRA. After power-up, 10 s are required for the AUXDAC circuitry to settle. The AUXDAC is loaded by writing to register AUXDAC. When the AUXDAC is in power-down mode, the AUXDAC register will retain its contents. When the AUXDAC is reset, the AUXDAC register will be set to all zeroes, leading to a voltage of 2 x VREFCAP/32 on the analog output.
The pin RESETB resets all the control registers. All registers except ASCLKRATE and BSCLKRATE are reset to zero. On reset, ASCLKRATE and BSCLKRATE are set to 4 so that the frequency of ASCLK and BSCLK is MCLK/8. As well as resetting the control registers using the reset pin, these registers can be reset using the reset bits in the baseband and auxiliary registers. All the auxiliary registers can be reset by taking the bit ARESET in control register ACRB high. The baseband registers can be reset by taking bit BRESET in baseband control register BCRA high. This is illustrated in Table IV. After resetting, the bits ARESET and BRESET will reset to zero. A reset using ARESET or BRESET requires 4 MCLK cycles. The registers ARDADDR, BRDADDR, ASCLKRATE, and BSCLKRATE can only be reset using the reset pin RESETB--these registers cannot be reset using the above mentioned bits. A system reset (using BRESET) requires eight MCLK cycles. The functions of the control register bits are summarized in Table IV to Table X.
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REV. 0
AD7729
Table IV. Baseband and Auxiliary Registers Table V. Baseband Control Register A (BCRA)
Name Reserved Reserved Reserved IRxOFFSET QRxOFFSET Reserved Reserved RxDELAY1 RxDELAY2 ARDADDR BRDADDR Reserved AUXDAC Reserved Reserved Reserved Reserved Reserved ACRA ACRB BCRA BCRB Reserved Reserved Reserved ASCLKRATE BSCLKRATE
R/W
Address 000000 (0) 000001 (1) 000010 (2) 000011 (3) 000100 (4) 000101 (5) 000110 (6) 000111 (7) 001000 (8) 001001 (9) 001010 (10) 001011 (11) 001100 (12) 001101 (13) 001110 (14) 001111 (15) 010000 (16) 010001 (17) 010010 (18) 010011 (19) 010100 (20) 010101 (21) 010110 (22) 010111 (23) 011000 (24) 011001 (25) 011010 (26)
Reset
Bit BCRA0
Name MCLKDIV
Function MCLK Divider. When this bit is set to 0, the internal MCLK has the same value as the external MCLK. When this bit equals 1, the external MCLK is divided by 2 within the AD7729 so that the device operates at half the external clock frequency. Selects AutoCal when set to 1 and UserCal when set to 0. When set to 1, the Rx calibration operates in external mode i.e., the I and Q analog inputs remain connected to the pins during the Rx autocalibration routine. This bit, in conjunction with RxPOWER1, is used to reduce the analog current consumption of the ADCs. This bit, in conjunction with RxPOWER0, is used to reduce the analog current consumption of the ADCs. Power-on for the receive section of the AD7729. Baseband Reset.
R/W R/W
BRESET BRESET
R/W R/W R/W R/W R/W
BRESET BRESET SRESET SRESET ARESET
BCRA1 BCRA2
RxAUTOCAL RxEXTCAL
BCRA3
RxPOWER0
R/W R/W R/W R/W
ARESET ARESET BRESET BRESET
BCRA4
RxPOWER1
BCRA5 BCRA6 SRESET SRESET BCRA7 BCRA8 BCRA9
Reserved RxON BRESET Reserved Reserved
R/W R/W
BRESET: can be reset using pin RESETB or bit BRESET. ARESET: can be reset using pin RESETB or bit ARESET. SRESET: only the pin RESETB can reset these registers.
Table VI. Power Modes for the ADCs
RxPOWER1 0 0 1 1
RxPOWER0 0 1 0 1
AIDD1 Reduction Reserved 1/3 (Power Mode 1) 2/5 (Power Mode 2) Reserved
Bits RxPOWER0 and RxPOWER1 are used to reduce the analog current consumption of the ADCs. The part is specified in Power Mode 1. In Power Mode 2, the MCLK needs to be less than 10 MHz. The performance of the part will then be comparable to the performance in Power Mode 1 except that the ADC current will now be less than 9.5 mA.
Table VII. Receive Section Activation
RxON Pin 0 0 1 1
RxON Bit 0 1 0 1
Receive Section OFF ON ON ON
REV. 0
-13-
AD7729
Table VIII. Baseband Control Register B (BCRB)
15 14 13 12 11 10 9 8 7 6 5 4 A4 3 A3 2 A2 1 A1 0 A0
Bit BCRB0 BCRB1 BCRB2 BCRB3 BCRB4
Name Reserved Reserved RU LP RxSPORTSEL
Function
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A5
Figure 19. Write Operation Frame Format
REFOUT Use. Reference Low Power. Selects the SPORT that will provide RxDATA when RxON is asserted. When set to 0, the BSPORT is selected and, when set to 1, the ASPORT is selected.
Reading Over the Baseband (or Auxiliary) SPORT
BCRB5 BCRB6 BCRB7 BCRB8 BCRB9
Reserved Reserved Reserved Reserved Reserved
To read the contents of a register, the address of the appropriate register is written to the read address register, ARDADDR or BRDADDR. The time interval between writing to the read address register and the frame synchronization signal becoming active equals 4 MCLK cycles. The read address register is 6 bits wide and Bits D11 to D6 of the input frame are used to write to this register, Bits D12 to D15 being don't cares, as shown in Figure 20. The frame format for reading is identical to that for writing i.e., 10 bits of data followed by 6 address bits corresponding to the source address of the data (with the exception of the Rx data).
15 14 X 13 X 12 X 11 10 9 8 7 6 5 0 4 0 3 1 2 0 1 1 0 0
Table IX. Auxiliary Control Register A (ACRA)
X
RA5 RA4 RA3 RA2 RA1 RA0
Bit ACRA0 ACRA1 ACRA2 ACRA3 ACRA4 ACRA5 ACRA6 ACRA7 ACRA8 ACRA9
Name Reserved Reserved AUXDACON Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Function
Figure 20. Writing to the Read Address Register (BRDADDR Shown Here)
Receiving RxDATA
Power On for Auxiliary DAC
Table X. Auxiliary Control Register B (ACRB)
The Rx ADC is activated by taking either the RxON bit or the RxON pin high. In this mode, Rx data is automatically output on the SDO pin of the SPORT at a word rate of 270 kHz for each of I and Q, after a delay of T1 + T2 + T3 (see Figure 16). The data format is I followed by Q. The AD7729 will output 16 bits of data, the 15-bit I or Q word, which is in twos complement format, and a flag bit. This flag bit (LSB) distinguishes between the I and Q words, the bit being at 0 when the word being output is an I word while this bit is at 1 when the output is a Q word. When RxON is taken high, the serial clock will have a frequency of 13 MHz, irrespective of the value in the clock rate register. When the AD7729 is ready to output Rx data, an output frame synchronization signal is generated and the Rx data is automatically output on the SDO pin, an I and Q word being output every 48 MCLK cycles (see Figure 17). Data can be output on the ASPORT or the BSPORT, bit RxSPORTSEL in control register BCRB being used to select the SPORT. Rx data can be received on one SPORT only, the user cannot interchange from one SPORT to the other.
MICROPROCESSOR INTERFACING
Bit ACRB0 ACRB1 ACRB2 ACRB3 ACRB4 ACRB5 ACRB6 ACRB7 ACRB8 ACRB9
Name ARESET Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Function Resets the Auxiliary Converter
Writing Over the Baseband (or Auxiliary) SPORT
Writing to and reading from registers via the SPORT involves the transfer of 16 bit words, 10 bits of data and 6 bits of address (with the exception of the Rx data). The frame format is as shown in Figure 19, Bit 15 being the first input bit of the frame. The destination of the 10-bit data is determined by the 6-bit destination address as indicated in Figure 19. Note that some registers are read only and, hence, cannot be written to.
The AD7729 has a standard serial interface which allows the user to interface the part to several DSPs. In all cases, the AD7729 operates as the master with the DSP acting as the slave. The AD7729 provides its own serial clock to clock the serial data/control information to/from the DSP.
AD7721-to-ADSP-21xx Interface
Figure 21 shows the AD7729 interface to the ADSP-21xx. For the ADSP-21xx, the bits in the serial port control register should be set up as TFSR = RFSR = 1 (a frame sync is needed for each transfer), SLEN = 15 (16-bit word length), TFSW = RFSW = 0 (normal framing), INVTFS = INVRFS = 0 (active high frame sync signals), IRFS = 0 (external RFS), ITFS = 1 (internal TFS) and ISCLK = 0 (external serial clock). REV. 0
-14-
AD7729
Grounding and Layout
ADSP-21xx
DR SDO
AD7729
RFS
SDOFS
SCLK
SCLK
TFS
SDIFS
DT
SDI
Figure 21. AD7729 to ADSP-21xx Interface
AD7729-to-TMS320C5x Interface
Since the analog inputs to the AD7729 are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent Common-Mode Rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies of the AD7729 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. The digital filters following the ADCs will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator. However, because the resolution of the AD7729 ADCs is high and the noise levels from the AD7729 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7729 should be designed so that the analog and digital sections are separated and confined to certain sections of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7729 is the only device requiring an AGND-to-DGND connection, the ground planes should be connected at the AGND-and-DGND pins of the AD7729. If the AD7729 is in a system where multiple devices require AGNDto-DGND connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7729. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7729 to avoid noise coupling. The power supply lines to the AD7729 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important when using high speed devices. All analog and digital supplies should be decoupled to AGND and DGND respectively with 0.1 F ceramic capacitors in parallel with 10 F tantalum capacitors. To achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD7729, it is recommended that the system's AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD7729 and AGND and the recommended digital supply decoupling capacitors between the DVDD pins and DGND.
Figure 22 shows the interface between the AD7729 and the TMS320C5x DSP. The TMS320C5x is configured as follows: MCM = 0 (CLKX is an input), TXM = 1 (the transmit frame sync signal is generated by the DSP), FSM = 1 (a frame sync is required for each transfer), FO = 0 (16-bit word length).
TMS320C5x
DR SDO
AD7729
FSR CLKR
SDOFS
SCLK CLKX FSX SDIFS
DX
SDI
Figure 22. AD7729 to TMS320C5x Interface
Power-Down
Each section of the AD7729 can be powered down. The Rx ADCs and the auxiliary DAC can be powered down individually by setting the appropriate bits in the control registers. When each section is powered up, time must be allowed so that the analog and digital circuitry can settle and, also, time is needed for the reference REFCAP to power up. To reduce this powerup time, Bit LP can be set to 1 so that when the ADCs and DAC are powered down, the reference REFCAP remains powered up by setting Bit LP to 1. Therefore, because the reference is powered up, the time needed for circuitry to settle when a section is powered up is reduced considerably since the reference does not require time to power up and settle. When all sections of the AD7729 are powered down, including the reference, the MCLK is stopped after 64 clock periods following the detection of the low power state. The MCLK reactivates when the AD7729 is communicated with, i.e., the SPORTs are activated, RxON is taken high, etc.
REV. 0
-15-
AD7729
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Small Outline (SOIC) (R-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0500 (1.27) 0.0192 (0.49) 0 0.0157 (0.40) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
28-Lead Thin Shrink Small Outline (TSSOP) (RU-28)
0.386 (9.80) 0.378 (9.60)
28 15
0.177 (4.50) 0.169 (4.30)
1
14
PIN 1 0.006 (0.15) 0.002 (0.05)
0.256 (6.50) 0.246 (6.25)
0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
SEATING PLANE
0.0256 (0.65) BSC
8 0
0.028 (0.70) 0.020 (0.50)
-16-
REV. 0
PRINTED IN U.S.A.
C3319-8-11/98

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